The semiconductor industry has experienced technological advances that have permitted increases in density and/or complexity of semiconductor memory devices. Also, the technological advances have allowed decreases in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend to employ and/or fabricate advanced semiconductor memory devices using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Silicon-on-insulator (SOI) and bulk substrates are examples of materials that may be used to fabricate such semiconductor memory devices. Such semiconductor memory devices may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (e.g., double, triple gate, or surrounding gate), and Fin-FET devices.
A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating body region wherein electrical charge may be stored. When excess majority electrical charges carriers are stored in the electrically floating body region, the memory cell may store a logic high (e.g., binary “1” data state). When the electrical floating body region is depleted of majority electrical charge carriers, the memory cell may store a logic low (e.g., binary “0” data state). Also, a semiconductor memory device may be fabricated on silicon-on-insulator (SOI) substrates or bulk substrates (e.g., enabling body isolation). For example, a semiconductor memory device may be fabricated as a three-dimensional (3-D) device (e.g., a multiple gate device, a Fin-FET device, and a vertical pillar device).
In one conventional technique, the memory cell of the semiconductor memory device may be read by applying bias signals to a source/drain region and a gate of the memory transistor. As such, a conventional reading technique may involve sensing an amount of current provided/generated by/in the electrically floating body region of the memory cell in response to the application of the source/drain region and gate bias signals to determine a data state of the memory cell. For example, the memory cell may have two or more different current states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: a binary “0” data state and a binary “1” data state).
In another conventional technique, the memory cell of the semiconductor memory device may be written to by applying bias signals to the source/drain region(s) and the gate of the memory transistor. As such, a conventional writing technique may result in an increase/decrease of majority charge carriers in the electrically floating body region of the memory cell which, in turn, determines the data state of the memory cell. Such an excess of majority charge carriers may result from channel impact ionization, band-to-band tunneling (gate-induced drain leakage “GIDL”), or direct injection. Majority charge carriers may be removed via drain region hole removal, source region hole removal, or drain and source region hole removal, for example, using back gate pulsing.
Often, conventional reading and/or writing operations may lead to relatively large power consumption and large voltage potential swings which may cause disturbance to unselected memory cells in the semiconductor memory device. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of majority charge carriers in the electrically floating body region of the memory cell, which, in turn, may result in an inaccurate determination of the data state of the memory cell. Furthermore, in the event that a bias signal having a voltage potential that is below a threshold voltage potential of the memory transistor is applied to the gate of the memory transistor, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may combine with majority charge carriers, which may be attracted to the gate as a result of the applied bias signal. As a result, the net quantity of majority charge carriers in the electrically floating body region may be reduced. This phenomenon, which is typically characterized as charge pumping, is problematic because the net quantity of majority charge carriers may be reduced in the electrically floating body region of the memory cell, which, in turn, may result in an inaccurate determination of the data state of the memory cell.
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional techniques for operating a semiconductor memory device.